An Overview of the PowerPC Platform

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This article provides an overview of the PowerPC Platform (PPCP) (formerly known as CHRP).

NOTE: The information discussed in this article is based on features and functionality planned for a future release. The discussion of PPCP herein does not represent a commitment on the part of Apple Computer, Inc. for providing or shipping the features and functionality discussed. Information is subject to change without notice.

Definitions

The following definitions are taken from the article titled "PowerPC Browser's Glossary." This article contains a glossary of PowerPC industry-related key terms and concepts. Terms are provided on newer PowerPC technology and important historically PC information leading up to the PowerPC. It is excerpted from the book, "Inside the PowerPC Revolution," written by Jeff Duntemann and Ron Pronk. The contents of the file is copyrighted by The Coriolis Group, Inc. The book, which covers the emerging PowerPC industry, is published by The Coriolis Group; ISBN: 1-883577-04-7; (602) 483-0192.

Bi-endian

There are two possible byte ordering conventions for representing scalar (that is, non-string) quantities in system memory. Big-endian byte ordering places the most significant byte of the scalar at the lowest memory address, whereas little-endian byte ordering places the least significant byte of the scalar at the lowest memory address. Virtually all CPUs support either one convention or the other, but a CPU that can be configured to handle both schemes is called bi-endian. The PowerPC is bi-endian in nature, which allows it to execute both big-endian 680x0 binaries and little-endian x86 binaries under emulation, without running afoul of byte-ordering conflicts.

Big-endian

A term specifying a byte-ordering convention for scalar data items. In the big-endian scheme, the most significant byte of a scalar is stored at the lowest memory address, the next most significant byte of the scalar is stored at the next higher address, and so on. The Motorola 680x0 line of CPUs is big-endian in nature. The PowerPC, while defaulting on power-up to big-endian mode, is in fact bi-endian and can operate either in big-endian or little-endian mode as required.

Little-endian

A term specifying a byte-ordering convention for scalar data items. In the little-endian scheme, the least significant byte of a scalar is stored at the lowest memory address, the next most significant byte of the scalar is stored at the next higher address, and so on. The Intel x86 line of CPUs is little-endian in nature, while most other industry CPUs are big-endian.

NOTE: The following information is taken from "PowerPC Microprocessor Common Hardware Reference Platform: A System Architecture", which is available from the PPCP Web Site:

http://chrp.apple.com/

What is PPCP?

The PowerPC Platform (PPCP) architecture specification provides a comprehensive computer system hardware-to-software interface definition, combined with minimum system requirements, that enables the development of and software porting to a range of compatible industry-standard computer systems from portables through servers.

These systems are based on the PowerPC microprocessor, as defined in The PowerPC Architecture. The definition supports the development of both uniprocessor and multiprocessor system implementations.

A key attribute and benefit of the architecture is the ability of hardware platform developers to have degrees of freedom of implementation below the level of architected interfaces and creating an opportunity for adding unique value. This flexibility is achieved through architecture facilities including:

device drivers
Open Firmware (OF)
Run-Time Abstraction Services (RTAS)
hardware abstraction layers

Though the PowerPC microprocessor is the most widely used RISC processor, substantial legacy software exists and a mechanism for running the bulk of this legacy software is a requirement. The system address map has been defined with a specific objective of assisting efficient x86 emulation.

Additionally the PowerPC microprocessors support Bi-Endian operation which is a key attribute important to running the supported operating systems and applications. Bi-Endian capability is not available in the current IBM PC compatible x86-based system architecture.

The architecture combines leading-edge IBM PC and Apple Macintosh technologies to create a superior personal computing platform. By design, it supports a wide range of computing needs including personal productivity, engineering design, data management, information analysis, education, desktop publishing, multimedia, entertainment, and database, file, and application servers.

The architecture effectively leverages industry-standard I/0 through the PCI bus while accommodating legacy I/0 from both the IBM PC compatible and the Apple Macintosh domains.

This approach provides several key benefits for system manufacturers and end customers:

systems can be designed and manufactured to enable the customer a choice of operating system support which could include AIX, Mac OS, NetWare, OS/2, Solaris or Windows NT
smooth application, operating system and customer system transitions are enabled by accommodation for legacy software, I/0 devices, and peripherals.

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